Open source hardware accelerator subsystem for FPGA/ASICs, by Antmicro

Jul 4, 2022

Antmicro published a new article entitled “Open source hardware accelerator subsystem for FPGA/ASICs”.

In this blog post, Antmicro describes their open source hardware accelerator subsystem for FPGA / ASICs that is being developed as part of the VEDLIoT project. The subsystem was designed to accommodate one of the key requirements of the broader SoC system that is VEDLIoT’s objective, i.e. to enable the use of efficient and low power accelerators. It is configurable, vendor independent and open source. The system reuses Antmicro’s open source components like e.g. FastVDMA data movers, along with the Linux drivers allowing users to easily integrate the subsystem with their solutions. The article outlines the process of creating this subsystem, its functions and potential applications. Links to code repositories and instructions on how to reproduce the examples are also provided.